module flashdecode4_7(clk50m,reset,HEX0);
input clk50m,reset;
output [0:6] HEX0;
reg [25:0] cnt;
reg [3:0] clk2;
reg clk1;
wire [3:0] addr3,addr2,addr1,addr0;

always @(posedge clk50m or negedge reset) begin
if(!reset) begin 
	cnt<=0;
end
else if(cnt==26'd50000000)
	begin cnt<=0;clk1<=~clk1;end
else 
	cnt<=cnt+1;
end

always @(posedge clk1 or negedge reset)begin
if(!reset) 
	clk2<=4'd0;
else if(clk2==4'd9)
	clk2<=4'd0;
else
	clk2<=clk2+1'b1;
end
assign { addr3,addr2,addr1,addr0}=clk2;
flash_decode  u1(addr0, HEX0);

endmodule

module flash_decode(ST,HEX);
input [3:0]ST;
output reg[0:6] HEX;

always @(*) begin
case(ST)
4'b0000: HEX=~7'b1111110;
4'b0001: HEX=~7'b0110000;
4'b0010: HEX=~7'b1101101;
4'b0011: HEX=~7'b1111001;
4'b0100: HEX=~7'b0110011;
4'b0101: HEX=~7'b1011011;
4'b0110: HEX=~7'b1011111;
4'b0111: HEX=~7'b1110000;
4'b1000: HEX=~7'b1111111;
4'b1001: HEX=~7'b1111011;
4'b1010: HEX=~7'b1110111;
4'b1011: HEX=~7'b0011111;
4'b1100: HEX=~7'b1001110;
4'b1101: HEX=~7'b0111101;
4'b1110: HEX=~7'b1001111;
4'b1111: HEX=~7'b0000000;
endcase
end

endmodule